Buried etch stops are often incorporated in interconnect structures, that are part of integrated circuits and microelectronic devices. Interconnect structures comprise metal lines positioned in line level interlayer dielectrics and vias positioned in via level interlayer dielectrics. Interconnect structures provide electrical communication between the multiple conductive layers of integrated circuits and microelectronic devices. Buried etch stop layers having low dielectric constants, thermal stability, and chemical contrast from other patterning dielectric layers allow for the generation of reliable interconnect structures and leads to enhanced device performance.
Buried etch stop layers should be definable by conventional dry etching processes, e.g. reactive ion etch (RIE), and should have compositions that provide chemical contrast to other layers. Additionally, it is advantageous for buried etch stop layers to exhibit thermal stability during high temperature processing and have sufficient adhesion to adjacent layers to withstand planarizing steps and other processes that produce stress on the interconnect structure. Further, the dielectric constant of the buried etch stop layer should be low in order to minimize resistance-capacitance (RC) delays and enhance performance. Buried etch stop layers may need to be permeable to the decomposition of products generated in porous dielectric systems in order to allow out-diffusion of these moieties. Finally, they should be capable of being processed in a cost effective manner.
For buried etch stop layers in interconnect structures having interlayer dielectrics deposited by spin-on-techniques it is advantageous that the buried etch stop layers also be deposited using spin-on techniques in order to decrease process time and cost. When the above layers are all deposited using spin-on-techniques, thermal annealing of the via and line layers may be performed simultaneously with the thermal curing of the buried etch stop.
The application of spin-on dielectrics as buried etch stops has been proposed; however, current implementations have been primarily limited to silsequioxanes, siloxanes, and other related chemistries that are primarily based on silicon-oxygen bonds. One potential drawback of these current implementations is poor etch selectivity with other dielectric layers. In particular, these systems may not exhibit sufficient etch selectivity to silicon carbonitrides, silicon carbides, and silicon nitrides that are commonly used as cap barrier layers. The lack of etch selectivity with these layers precludes the generation of integrated circuits in a controllable manner.
What is needed is a process for forming a buried etch stop in an interconnect structure, where the buried etch stop composition reduces manufacturing costs; produces reliable interconnect structures; and enhances device performance. What is further needed is an interconnect structure where the buried etch stop layer composition has a low dielectric constant; thermal stability; and chemical contrast which facilitates etch processing between other patterning layers.